LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 1243

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Freescale Semiconductor

Load capacitance C

Thresholds for delay measurement points

Timing speciﬁed for equal load on all SPI output pins. Avoid asymmetric load.

1. If conﬁgured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.

the timing diagram for master mode with transmission format CPHA = 0 is depicted.

on all outputs

MC9S12XE-Family Reference Manual Rev. 1.23

Figure A-7. SPI Master Timing (CPHA = 0)

Table A-27. Measurement Conditions

Bit MSB-1. . . 1

(20% / 80%) V

Full drive mode

Appendix A Electrical Characteristics