LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 263

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5.2.2
This mode is used for emulation systems in which the target application is operating in normal expanded
mode.
If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals
UDS, LDS, RE, and WE from the ADDR0, LSTRB, and RW signals.
Figure 5-6
The timings of accesses with 1 stretch cycle are shown in
The associated timing numbers are given in
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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ECLKX2 rising edges have the same timing as ECLK edges.
The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing
for an external non-PRR access with 1 cycle of stretch as shown in example 2b.
Figure ‘Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle’
Figure ‘Example 2b: Emulation Expanded Mode — Write with 1 Stretch Cycle’
shows the PRU connection with the available external bus signals in an emulator application.
Example 2b: Emulation Expanded Mode
ADDR[22:20]/ACC[2:0]
ADDR[22:0]/IVD[15:0]
Figure 5-6. Application in Emulation Expanded Mode
S12X_EBI
MC9S12XE-Family Reference Manual Rev. 1.23
ADDR[19:16]/
IQSTAT[3:0]
DATA[15:0]
ECLKX2
CS[3:0]
LSTRB
EWAIT
ECLK
RW
EMULMEM
PRU
Emulator
PRR
UDS
LDS
WE
RE
Chapter 5 External Bus Interface (S12XEBIV4)
Ports
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