LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 370

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
10.3.1.10 XGATE Semaphore Register (XGSEM)
The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and
the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by
the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM
instructions. The S12X_CPU has access to the semaphores through the XGATE Semaphore Register
(Figure
Module Base +0x0001A
Read: Anytime
Write: Anytime (see
370
XGSWTM[7:0]
Reset
XGSWT[7:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
R
Field
15–8
7–0
10-12). Refer to section
15
0
0
Software Trigger Mask — These bits control the write access to the XGSWT bits. Each XGSWT bit can only
be written if a "1" is written to the corresponding XGSWTM bit in the same access.
Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSWT in the same bus cycle
1 Enable write access to the corresponding XGSWT bit in the same bus cycle
Software Trigger Bits — These bits act as interrupt flags that are able to trigger XGATE software channels.
They can only be set and cleared by software.
Read:
0 No software trigger pending
1 Software trigger pending if the XGIE bit is set
Write:
0 Clear Software Trigger
1 Set Software Trigger
14
0
0
The XGATE channel IDs that are associated with the eight software triggers
are determined on chip integration level. (see Section “Interrupts“ of the
device overview)
XGATE software triggers work like any peripheral interrupt. They can be
used as XGATE requests as well as S12X_CPU interrupts. The target of the
software trigger must be selected in the S12X_INT module.
13
0
0
Section 10.4.4,
XGSEMM[7:0]
12
0
0
Figure 10-12. XGATE Semaphore Register (XGSEM)
MC9S12XE-Family Reference Manual , Rev. 1.23
Section 10.4.4, “Semaphores”
11
Table 10-11. XGSWT Field Descriptions
0
0
“Semaphores”)
10
0
0
0
0
9
NOTE
0
0
8
Description
0
7
for details.
6
0
0
5
XGSEM[7:0]
0
4
0
3
Freescale Semiconductor
0
2
1
0
0
0