LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 228
LFEBS12UB
Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Specifications of LFEBS12UB
Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 3 Memory Mapping Control (S12XMMCV4)
3.5.3.4
In emulation expanded mode the external bus will be connected to the emulator and to the application. If
the ROMON bit is set, the internal FLASH provides the data. If the EROMON bit is set as well the
emulator observes all CPU internal actions, otherwise the emulator provides the data and traces all CPU
actions (see
the emulator will observe the CPU internal actions (see
228
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Figure
ROM Control in Emulation Expanded Mode
3-27). When the ROMON bit is cleared, the application memory provides the data and
MCU
MCU
Figure 3-27. ROMON = 1 in Emulation Expanded Mode
MC9S12XE-Family Reference Manual , Rev. 1.23
Flash
Figure
Emulator
Application
Emulator
Application
3-28).
EROMON = 0
EROMON = 1
Memory
Memory
Flash
Observer
Generator
Freescale Semiconductor
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