LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 364

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10 XGATE (S12XGATEV3)
Module Base +0x0002
Read: Anytime
Write: In Debug Mode
10.3.1.3
The XGATE Channel Priority Level Register
In debug mode this register can be used to select a priority level when launching a thread (see
Section 10.6.1, “Debug
Module Base +0x0003
Read: Anytime
Write: In Debug Mode
10.3.1.4
The XGATE Initial Stack Pointer Select Register
to address “Module Base +0x0006”. A value of zero selects the Vector Base Register (XGVBR). Setting
1. Refer to
364
XGCHID[6:0]
XGCHPL[2:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Reset
Reset
Field
Field
6–0
2-0
W
W
R
R
Section 10.6.1, “Debug
Request Identifier — ID of the currently active channel
Priority Level— Priority level of the currently active channel
XGATE Channel Priority Level (XGCHPL)
XGATE Initial Stack Pointer Select Register (XGISPSEL)
0
0
0
0
7
7
Figure 10-5. XGATE Channel Priority Level Register (XGCHPL)
1
1
Features”).
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
6
6
Figure 10-4. XGATE Channel ID Register (XGCHID)
Features”
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 10-4. XGCHPL Field Descriptions
Table 10-3. XGCHID Field Descriptions
0
0
0
5
5
(Figure
(Figure
0
0
0
4
4
Description
10-5) shows the priority level of the current thread.
Description
XGCHID[6:0]
10-6) determines the register which is mapped
0
0
0
3
3
0
0
2
2
XGCHPL[2:0]
Freescale Semiconductor
0
0
1
1
0
0
0
0