LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 160

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x0272

Address 0x0273

Write: Anytime.

Port AD0 data direction—

This register controls the data direction of pins 15 through 8.

1 Associated pin is conﬁgured as output.

0 Associated pin is conﬁgured as input.

Port AD0 Data Direction Register 0 (DDR0AD0)

Port AD0 Data Direction Register 1 (DDR1AD0)

Due to internal synchronization circuits, it can take up to 2 bus clock cycles

until the correct value is read on PT0AD0 registers, when changing the

DDR0AD0 register.

To use the digital input function on Port AD0 the ATD Digital Input Enable

Figure 2-69. Port AD0 Data Direction Register 0 (DDR0AD0)

Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0)

Table 2-67. DDR0AD0 Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Access: User read/write

Freescale Semiconductor