LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 905

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The FCLKDIV register is used to control timed events in program and erase algorithms.

All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.

Freescale Semiconductor

Offset Module Base + 0x0000

Clock Divider Loaded

0 FCLKDIV register has not been written

1 FCLKDIV register has been written since the last reset

Clock Divider Bits — FDIV[6:0] must be set to effectively divide OSCCLK down to generate an internal Flash

clock, FCLK, with a target frequency of 1 MHz for use by the Flash module to control timed events during program

and erase algorithms.

Please refer to

Flash Clock Divider Register (FCLKDIV)

The FCLKDIV register should never be written while a Flash command is

executing (CCIF=0). The FCLKDIV register is writable during the Flash

reset sequence even though CCIF is clear.

= Unimplemented or Reserved

Section 25.4.1, “Flash Command Operations,”

Figure 25-4. FTM256K2 Register Summary (continued)

Figure 25-5. Flash Clock Divider Register (FCLKDIV)

= Unimplemented or Reserved

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 25-8. FCLKDIV Field Descriptions

shows recommended values for FDIV[6:0] based on OSCCLK frequency.

Chapter 25 256 KByte Flash Module (S12XFTM256K2V1)

for more information.