LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 365

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

this register to a channel priority level (non-zero value) selects the corresponding Initial Stack Pointer
Registers XGISP74 or XGISP31 (see
Module Base +0x0005
Read: Anytime
Write: Anytime
10.3.1.5
The XGISP74 register is intended to point to the stack region that is used by XGATE channels of priority
7 to 4. Every time a thread of such priority is started, RISC core register R7 will be initialized with the
content of XGISP74.
Module Base +0x0006
Read: Anytime
Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
Freescale Semiconductor
XGISPSEL[1:0]
Reset
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Reset
Field
W
R
1-0
W
R
15
0
Register select— Determines whether XGISP74, XGISP31, or XGVBR is mapped to “Module Base +0x0006”.
See
XGATE Initial Stack Pointer for Interrupt Priorities 7 to 4 (XGISP74)
Figure 10-7. XGATE Initial Stack Pointer for Interrupt Priorities 7 to 4 (XGISP74)
0
0
7
14
0
Table
= Unimplemented or Reserved
Figure 10-6. XGATE Initial Stack Pointer Select Register (XGISPSEL)
13
0
10-6.
XGISPSEL[1:0]
= Unimplemented or Reserved
0
0
6
12
0
Table 10-6. XGISP74, XGISP31, XGVBR Mapping
3
2
1
0
MC9S12XE-Family Reference Manual Rev. 1.23
Table 10-5. XGISPSEL Field Descriptions
11
0
Table
0
0
5
10
0
Register Mapped to “Module Base +0x0006“
10-6).
0
9
XGISP74[15:1]
0
0
4
0
8
Description
Reserved
XGISP74
XGISP31
XGVBR
0
7
0
0
3
6
0
0
5
0
0
2
0
4
Chapter 10 XGATE (S12XGATEV3)
0
3
0
1
XGISPSEL[1:0]
0
2
1
0
0
0
0
0
0
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