LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 270

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 Interrupt (S12XINTV2)
6.3.2
This section describes in address order all the XINT module registers and their individual bits.
270
Address
0x012C INT_CFDATA4 R
0x012D INT_CFDATA5 R
0x0121
0x0126
0x0127
0x0128 INT_CFDATA0 R
0x0129 INT_CFDATA1 R
0x012A INT_CFDATA2 R
0x012B INT_CFDATA3 R
0x012E INT_CFDATA6 R
0x012F INT_CFDATA7 R
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
INT_CFADDR
INT_XGPRIO
Register
Register Descriptions
Name
IVBR
W
W
W
W
W
W
W
W
W
W
W
R
R
R
RQST
RQST
RQST
RQST
RQST
RQST
RQST
RQST
Bit 7
0
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 6-2. XINT Register Summary
= Unimplemented or Reserved
INT_CFADDR[7:4]
6
0
0
0
0
0
0
0
0
0
5
0
0
0
0
0
0
0
0
0
IVB_ADDR[7:0]7
4
0
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
0
0
2
0
Freescale Semiconductor
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
XILVL[2:0]
1
0
Bit 0
0