LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 31

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.1.2
Memory map and bus interface modes:
Low-power modes:
Operating system states
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Low-power wake-up timer (API)
— Available in all modes including Full Stop Mode
— Trimmable to +-5% accuracy
— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution
Input/Output
— Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins
— Hysteresis and configurable pull up/pull down device on all input pins
— Configurable drive strength on all output pins
Package Options
— 208-pin MAPBGA
— 144-pin low-profile quad flat-pack (LQFP)
— 112-pin low-profile quad flat-pack (LQFP)
— 80-pin quad flat-pack (QFP)
50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency
Normal and emulation operating modes
— Normal single-chip mode
— Normal expanded mode
— Emulation of single-chip mode
— Emulation of expanded mode
Special Operating Modes
— Special single-chip mode with active background debug mode
— Special test mode (Freescale use only)
System stop modes
— Pseudo stop mode
— Full stop mode with fast wake-up option
System wait mode
Supervisor state
User state
Modes of Operation
MC9S12XE-Family Reference Manual Rev. 1.23
Chapter 1 Device Overview MC9S12XE-Family
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