LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 485

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The COP time-out period is restarted if one these two conditions is true:
Freescale Semiconductor
WRTMASK
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
RSBCK
CR[2:0]
WCOP
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with
2. Changing RSBCK bit from “0” to “1”.
Field
2–0
7
6
5
WRTMASK = 0.
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts
and the user must wait until the next window before writing to ARMCOP.
window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL
1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL.
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see
nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out
causes a system reset. This can be avoided by periodically (before time-out) reinitialize the COP counter via the
ARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (
or
(Does not count for “write once”.)
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in emulation or special modes
CR2
0
0
0
0
1
1
1
MC9S12XE-Family Reference Manual Rev. 1.23
Table 11-12. COPCTL Field Descriptions
2
24
Table 11-13. COP Watchdog Rates
CR1
cycles) in normal COP mode (Window COP mode disabled):
0
0
1
1
0
0
1
CR0
0
1
0
1
0
1
0
Description
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Cycles to Timeout
COP disabled
OSCCLK
2
2
2
2
2
2
14
16
18
20
22
23
(1)
Table 11-13
shows the duration of this
Table
11-13). Writing a
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