LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 569

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Bus Clock
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
P0
P1
P2
P3
P4
P5
P6
P7
Timer Prescaler
÷ 1, 2, ..., 128
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Pin Logic
Figure 14-67. Detailed Timer Block Diagram in Latch Mode when PRNT = 0
EDG0
EDG1
EDG2
EDG3
SH04
SH15
EDG4
EDG5
EDG6
EDG7
SH37
SH26
Counter
Counter
Counter
Counter
Delay
Delay
Delay
Delay
MC9S12XE-Family Reference Manual Rev. 1.23
MUX
MUX
MUX
MUX
16 BIT MAIN TIMER
16-Bit Free-Running
EDG1
EDG2
EDG3
EDG0
Main Timer
TC0 Capture/Compare Reg.
TC1 Capture/Compare Reg.
TC2 Capture/Compare Reg.
TC3 Capture/Compare Reg.
TC4 Capture/Compare Reg.
TC5 Capture/Compare Reg.
TC6 Capture/Compare Reg.
TC7 Capture/Compare Reg.
Bus Clock
Comparator
TC0H Hold Reg.
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
Comparator
TC1H Hold Reg.
TC2H Hold Reg.
TC3H Hold Reg.
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Modulus Prescaler
÷ 1, 4, 8, 16
ICLAT, LATQ, BUFEN
to Modulus Counter
(Force Latch)
Write 0x0000
PA0H Hold Reg.
PA1H Hold Reg.
PA2H Hold Reg.
PA3H Hold Reg.
16-Bit Modulus
Down Counter
PAC0
PAC1
PAC2
PAC3
16-Bit Load Register
0
0
0
0
(MDC Latch Enable)
RESET
RESET
RESET
RESET
LATQ
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