LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 97

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Freescale Semiconductor
Port
S
T
Pin Name
PT[4:0]
PT[7]
PT[5]
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
Pin Function
& Priority
VREG_API
IOC[4:0]
MOSI0
MISO0
IOC[7]
IOC[5]
SCK0
RXD1
RXD0
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
TXD1
GPIO
GPIO
TXD0
GPIO
GPIO
SS0
(1)
MC9S12XE-Family Reference Manual , Rev. 1.23
I/O
I/O Enhanced Capture Timer Channels 7 input/output
I/O General-purpose I/O
I/O Enhanced Capture Timer Channel 5 input/output
I/O General-purpose I/O
I/O Enhanced Capture Timer Channels 4 - 0 input/output
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 slave select output in master mode,
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 serial clock pin
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 master out/slave in pin
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 master in/slave out pin
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
I/O General-purpose I/O
O VREG Autonomous Periodical Interrupt output
O Serial Communication Interface 1 transmit pin
O Serial Communication Interface 0 transmit pin
I
I
input in slave mode or master mode.
Serial Communication Interface 1 receive pin
Serial Communication Interface 0 receive pin
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
Pin Function
after Reset
GPIO
GPIO
97

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