LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 801

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.8
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0008
Module Base + 0x0009
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
OMx
OLx
7:0
7:0
W
W
R
R
OM7
OM3
Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For
Output Level — These eight pairs of control bits are encoded to specify the output action to be taken as a result
of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output
tied to OCx.
Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
0
0
7
7
an output line to be driven by an OCx the OCPDx must be cleared.
an output line to be driven by an OCx the OCPDx must be cleared.
OMx
OL7
OL3
0
0
6
6
0
0
1
1
Figure 22-14. Timer Control Register 1 (TCTL1)
Figure 22-15. Timer Control Register 2 (TCTL2)
Table 22-8. TCTL1/TCTL2 Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.23
Table 22-9. Compare Result Output Action
OM6
OM2
OLx
0
1
0
1
5
0
5
0
OL6
OL2
0
0
4
4
action on the timer output signal
Clear OCx output line to zero
Description
Set OCx output line to one
Toggle OCx output line
No output compare
Chapter 22 Timer Module (TIM16B8CV2) Block Description
OM5
OM1
Action
0
0
3
3
OL5
OL1
2
0
2
0
OM4
OM0
0
0
1
1
OL4
OL0
0
0
0
0
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