LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 189

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4.4
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
Freescale Semiconductor
2-104).
Pin interrupts
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
1. These values include the spread of the oscillator frequency over temper-
Figure 2-108. Interrupt Glitch Filter on Port P, H and J (PPS=0)
Uncertain
ature, voltage and process.
Ignored
Pulse
Valid
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 2-104. Pulse Detection Criteria
t
pign
t
pval
3 < t
(Figure
t
t
pulse
pulse
pulse
STOP
uncertain
< 4
≤ 3
≥ 4
2-109) shorter than a specified time from generating an
bus clocks
bus clocks
bus clocks
Unit
Mode
Chapter 2 Port Integration Module (S12XEPIMV1)
t
pign
STOP
< t
t
t
pulse
pulse
pulse
(1)
≤ t
< t
≥ t
pign
pval
pval
(Figure 2-108
and
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