LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 444
LFEBS12UB
Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Specifications of LFEBS12UB
Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 10 XGATE (S12XGATEV3)
ORL
Operation
RD.L | IMM8 ⇒ RD.L
Performs a bit wise logical OR between the low byte of register RD and an immediate 8 bit constant and
stores the result in the destination register RD.L. The high byte of RD is not affected.
CCR Effects
Code and CPU Cycles
444
N:
Z:
V:
C:
ORL RD, #IMM8
N
∆
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 7 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Z
∆
V
0
Source Form
—
C
Logical OR Immediate 8 bit Constant
MC9S12XE-Family Reference Manual , Rev. 1.23
Address
Mode
IMM8
1
(Low Byte)
0
1
0
0
Machine Code
RD
IMM8
Freescale Semiconductor
ORL
Cycles
P
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