LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 159

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Freescale Semiconductor

Address 0x0270

Address 0x0271

Write: Anytime.

Port AD0 general purpose input/output data—Data Register

This register is associated with ATD0 analog inputs AN[15:8] on PAD[15:8], respectively.

When not used with the alternative function, this pin can be used as general purpose I/O.

If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise

the buffered pin input state is read.

Port AD0 general purpose input/output data—Data Register

This register is associated with ATD0 analog inputs AN[7:0] on PAD[7:0], respectively.

When not used with the alternative function, these pins can be used as general purpose I/O.

If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise

the buffered pin input state is read.

Port AD0 Data Register 0 (PT0AD0)

Port AD0 Data Register 1 (PT1AD0)

Figure 2-67. Port AD0 Data Register 0 (PT0AD0)

Figure 2-68. Port AD0 Data Register 1 (PT1AD0)

Table 2-65. PT0AD0 Register Field Descriptions

Table 2-66. PT1AD0 Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Chapter 2 Port Integration Module (S12XEPIMV1)

Access: User read/write