LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 121

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source

2. Reset values in emulation modes are identical to those of the target mode.

Freescale Semiconductor

Address 0x001C (PRR)

is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Port B reduced drive—Select reduced drive for outputs

This bit conﬁgures the drive strength of all output pins as either full or reduced independent of the function used on

the pins. If a pin is used as input this bit has no effect.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

Port A reduced drive—Select reduced drive for outputs

This bit conﬁgures the drive strength of all output pins as either full or reduced independent of the function used on

the pins. If a pin is used as input this bit has no effect.

1 Reduced drive selected (approx. 1/5 of the full drive strength).

0 Full drive strength enabled.

ECLK Control Register (ECLKCTL)

= Unimplemented or Reserved

Table 2-15. RDRIV Register Field Descriptions (continued)

Figure 2-13. ECLK Control Register (ECLKCTL)

MC9S12XE-Family Reference Manual , Rev. 1.23

Chapter 2 Port Integration Module (S12XEPIMV1)

Access: User read/write