LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 805

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
22.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
Freescale Semiconductor
Module Base + 0x000E
Module Base + 0x000F
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
C[7:0]F
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7:0
W
W
R
R
C7F
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN or PAEN is set to
one.
When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel
(0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
TOF
0
0
7
7
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
Unimplemented or Reserved
C6F
0
0
0
6
6
Figure 22-20. Main Timer Interrupt Flag 1 (TFLG1)
Figure 22-21. Main Timer Interrupt Flag 2 (TFLG2)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 22-16. TRLG1 Field Descriptions
C5F
5
0
5
0
0
C4F
NOTE
0
0
0
4
4
Description
Chapter 22 Timer Module (TIM16B8CV2) Block Description
C3F
0
0
0
3
3
C2F
2
0
2
0
0
C1F
0
0
0
1
1
C0F
0
0
0
0
0
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