LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 313

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
DBGBRK
XGSBPE
COMRV
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
BDM
3–2
1–0
5
4
XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is
passed to the CPU12X. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can
request an CPU12X breakpoint depending on the state of this bit.
0 XGATE S/W breakpoint request is disabled
1 XGATE S/W breakpoint request is enabled
Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter
Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled
by the ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint
to either CPU12X or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the
breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is
generated immediately. Please refer to
independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the CPU12X independent
of the DBGBRK bit field configuration. See
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See
DBGBRK
COMRV
00
01
10
11
00
01
10
11
Table 8-5. DBGC1 Field Descriptions (continued)
No breakpoint generated
XGATE breakpoint generated
CPU12X breakpoint generated
Breakpoints generated for CPU12X and XGATE
MC9S12XE-Family Reference Manual Rev. 1.23
Visible Comparator
Comparator A
Comparator B
Comparator C
Comparator D
Table 8-6. DBGBRK Encoding
Table 8-7. COMRV Encoding
Section 8.4.7
Resource Halted by Breakpoint
Table
8-6.
Description
for further details. XGATE software breakpoints are
Visible Register at 0x0027
Table
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
Chapter 8 S12X Debug (S12XDBGV3) Module
8-7.
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