LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 451

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SIF
Operation
Sets the interrupt flag of an XGATE channel (XGIF). This instruction supports two source forms. If
inherent address mode is used, then the interrupt flag of the current channel (XGCHID) will be set. If the
monadic address form is used, the interrupt flag associated with the channel id number contained in
RS[6:0] is set. The content of RS[15:7] is ignored.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
SIF
SIF RS
N
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Not affected.
Not affected.
Not affected.
Not affected.
Z
V
Source Form
Interrupt flags of reserved channels (see Device User Guide) can’t be set.
C
MC9S12XE-Family Reference Manual Rev. 1.23
Address
Mode
MON
INH
Set Interrupt Flag
0
0
NOTE
0
0
0
0
0
0
0
0
0
Machine Code
RS
1
1
0
1
0
1
0
1
Chapter 10 XGATE (S12XGATEV3)
0
1
0
0
0
1
0
1
0
1
SIF
Cycles
PA
PA
451

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