LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 683

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.0.2
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0001
PFLMT[1:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PFLT[3:0]
PITSWAI
PITFRZ
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
PITE
1:0
3:0
7
6
5
W
R
PIT Module Enable Bit — This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and
flag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start down-
counting with the corresponding load register values.
0 PIT disabled (lower power consumption).
1 PIT is enabled.
PIT Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 PIT operates normally in wait mode
1 PIT clock generation stops and freezes the PIT module when in wait mode
PIT Counter Freeze while in Freeze Mode Bit — When during debugging a breakpoint (freeze mode) is
encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. The PITFRZ
bit controls the PIT operation while in freeze mode.
0 PIT operates normally in freeze mode
1 PIT counters are stalled when in freeze mode
PIT Force Load Bits for Micro Timer 1:0 — These bits have only an effect if the corresponding micro timer is
active and if the PIT module is enabled (PITE set). Writing a one into a PFLMT bit loads the corresponding 8-bit
micro timer load register into the 8-bit micro timer down-counter. Writing a zero has no effect. Reading these bits
will always return zero.
Note: A micro timer force load affects all timer channels that use the corresponding micro time base.
PIT Force Load Bits for Timer 3-0 — These bits have only an effect if the corresponding timer channel (PCE
set) is enabled and if the PIT module is enabled (PITE set). Writing a one into a PFLT bit loads the corresponding
16-bit timer load register into the 16-bit timer down-counter. Writing a zero has no effect. Reading these bits will
always return zero.
PIT Force Load Timer Register (PITFLT)
0
0
7
0
0
6
Figure 18-4. PIT Force Load Timer Register (PITFLT)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 18-2. PITCFLMT Field Descriptions
Table 18-3. PITFLT Field Descriptions
5
0
0
0
0
4
Description
Description
PFLT3
0
0
3
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
PFLT2
2
0
0
PFLT1
0
0
1
PFLT0
0
0
0
683