LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 111

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
2. Applicable only on Port P, H, and J.
Freescale Semiconductor
DDR
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IO
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
All register bits in this module are completely synchronous to internal
clocks during a register read.
RDR
0
0
1
1
0
0
1
1
x
x
x
x
x
x
x
PE
0
1
1
0
0
1
1
x
x
x
x
x
x
x
x
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 2-3. Pin Configuration Summary
PS
x
0
1
0
1
0
1
x
x
x
x
0
1
0
1
(1)
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(2)
NOTE
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Function
Chapter 2 Port Integration Module (S12XEPIMV1)
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull Device
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Interrupt
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