LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 123

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: See individual bit descriptions below.
1. Read: Always reads 0x00
2.3.17
2.3.18
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Freescale Semiconductor
Address 0x001E
Address 0x001F
Write: See individual bit descriptions below.
IRQEN
Write: Unimplemented
IRQE
Field
Reset
Reset
5-0
7
6
W
W
R
R
IRQ select edge sensitive only—
Special modes: Read or write anytime.
Normal & emulation modes: Read anytime, write once.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1
0 IRQ configured for low level recognition.
External IRQ enable—
Read or write anytime.
1 External IRQ pin is connected to interrupt logic.
0 External IRQ pin is disconnected from interrupt logic.
Reserved—
IRQE
IRQ Control Register (IRQCR)
PIM Reserved Register
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0
0
0
7
7
Writing to this register when in special modes can alter the pin functionality.
= Unimplemented or Reserved
= Unimplemented or Reserved
IRQEN
1
0
0
6
6
Table 2-17. IRQCR Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
Figure 2-15. IRQ Control Register (IRQCR)
Figure 2-16. PIM Reserved Register
0
0
0
0
5
5
NOTE
0
0
0
0
4
4
Description
3
0
0
3
0
0
Chapter 2 Port Integration Module (S12XEPIMV1)
0
0
0
0
2
2
Access: User read/write
0
0
0
0
1
1
Access: User read
0
0
0
0
0
0
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