LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 812

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 22 Timer Module (TIM16B8CV2) Block Description

The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select

the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

16-BIT COMPARATOR

TCNT(hi):TCNT(lo)

16-BIT COUNTER

PACNT(hi):PACNT(lo)

16-BIT COUNTER

Figure 22-30. Detailed Timer Block Diagram

MC9S12XE-Family Reference Manual Rev. 1.23

CLEAR COUNTER

DIVIDE-BY-64

channel 7 output

CH. 1 COMPARE

CH. 0 CAPTURE

CH. 1 CAPTURE

CH. 0COMPARE

CH. 7 COMPARE

CH.7 CAPTURE

Freescale Semiconductor