LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 437

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LSL
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
LSL RD, #IMM4
LSL RD, RS
N
∆
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Z
∆
old
V
∆
Source Form
^ RD[15]
C
∆
new
C
MC9S12XE-Family Reference Manual Rev. 1.23
Address
Mode
IMM4
DYA
Logical Shift Left
RD
0
0
n
0
0
0
0
0
0
1
1
Machine Code
RD
RD
0
0
n bits
RS
IMM4
0
Chapter 10 XGATE (S12XGATEV3)
0
1
1
0
1
1
0
0
LSL
0
0
Cycles
P
P
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