LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 192
LFEBS12UB
Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Specifications of LFEBS12UB
Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 3 Memory Mapping Control (S12XMMCV4)
3.1.1
3.1.2
The main features of this block are:
192
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
•
•
Unimplemented areas
Mis-aligned address
single-chip modes
Paging capability to support a global 8 Mbytes memory address space
Bus arbitration between the masters CPU, BDM and XGATE
external resource
expanded modes
emulation modes
Aligned address
External Space
global address
normal modes
special modes
Logic level “1”
Logic level “0”
local address
Bus Clock
Terminology
Features
MCU
NVM
word
PRR
PRU
byte
NS
NX
SS
ES
EX
ST
0x
x
Voltage that corresponds to Boolean true state
Voltage that corresponds to Boolean false state
Represents hexadecimal number
Represents logic level ’don’t care’
8-bit data
16-bit data
based on the 64 KBytes Memory Space (16-bit address)
based on the 8 MBytes Memory Space (23-bit address)
Address on even boundary
Address on odd boundary
System Clock. Refer to CRG Block Guide.
Normal Expanded Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Special Test Mode
Normal Single-Chip Mode
Special Single-Chip Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Normal Single-Chip Mode
Normal Expanded Mode
Special Single-Chip Mode
Special Test Mode
Normal Single-Chip Mode
Special Single-Chip Mode
Normal Expanded Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Special Test Mode
Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented
Area which is accessible in the global address range 14_0000 to 3F_FFFF
Resources (Emulator, Application) connected to the MCU via the external bus on
expanded modes (Unimplemented areas and External Space)
Port Replacement Registers
Port Replacement Unit located on the emulator side
MicroController Unit
Non-volatile Memory; Flash EEPROM or ROM
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 3-2. Acronyms and Abbreviations
Freescale Semiconductor
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