LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 169

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Freescale Semiconductor

Address 0x036A

Address 0x036B

Write: Anytime.

Port R data direction—

This register controls the data direction of pins 7 through 0.

The TIM forces the I/O state to be an output for each timer port associated with an enabled output compare. In this

case the data direction bits will not change.

The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is

The timer Input Capture always monitors the state of the pin.

1 Associated pin is conﬁgured as output.

0 Associated pin is conﬁgured as high-impedance input.

Port R Data Direction Register (DDRR)

Port R Reduced Drive Register (RDRR)

Due to internal synchronization circuits, it can take up to 2 bus clock cycles

until the correct value is read on PTR or PTIR registers, when changing the

DDRR register.

Figure 2-86. Port R Reduced Drive Register (RDRR)

Figure 2-85. Port R Data Direction Register (DDRR)

Table 2-83. DDRR Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Chapter 2 Port Integration Module (S12XEPIMV1)

Access: User read/write