LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 461

KIT STUDENT LEARNING S12 DG128

LFEBS12UB

Manufacturer Part Number
LFEBS12UB
Description
KIT STUDENT LEARNING S12 DG128
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of LFEBS12UB

Architecture
8/16-bit
Code Gen Tools Included
Code Warrior
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12D
Kit Contents
HCS12 DG128 Learning Kit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
XNORH
Operation
~(RD.H ^ IMM8) ⇒ RD.H
Performs a bit wise logical exclusive NOR between the high byte of register RD and an immediate 8 bit
constant and stores the result in the destination register RD.H. The low byte of RD is not affected.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
XNORH RD, #IMM8
N
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Z
V
0
Source Form
C
MC9S12XE-Family Reference Manual Rev. 1.23
Logical Exclusive NOR Immediate
Address
Mode
IMM8
8 bit Constant (High Byte)
1
0
1
1
1
Machine Code
RD
XNORH
Chapter 10 XGATE (S12XGATEV3)
IMM8
Cycles
P
461

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