LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 385

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.8.1.3
Operands for immediate mode instructions are included in the instruction stream and are fetched into the
instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an
immediate addressing mode operand. This address mode is used for semaphore instructions.
Examples:
10.8.1.4
The 4 bit wide immediate addressing mode is supported by all shift instructions.
RD = RD ∗ IMM4
Examples:
10.8.1.5
The 8 bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP).
RD = RD ∗ imm8
Examples:
10.8.1.6
The 16 bit wide immediate addressing mode is a construct to simplify assembler code. Instructions which
offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode.
RD = RD ∗ IMM16
Examples:
10.8.1.7
In this addressing mode only one operand is explicitly given. This operand can either be the source (f(RD)),
the target (RD = f()), or both source and target of the operation (RD = f(RD)).
Examples:
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CSEM
SSEM
LSL
LSR
ADDL
SUBL
LDH
CMPL
LDW
ADD
JAL
SIF
Immediate 3-Bit Wide (IMM3)
Immediate 4 Bit Wide (IMM4)
Immediate 8 Bit Wide (IMM8)
Immediate 16 Bit Wide (IMM16)
Monadic Addressing (MON)
#1
#3
R4,#1
R4,#3
R1,#1
R2,#2
R3,#3
R4,#4
R4,#$1234
R4,#$5678
R1
R2
; Unlock semaphore 1
; Lock Semaphore 3
; R4 = R4 << 1; shift register R4 by 1 bit to the left
; R4 = R4 >> 3; shift register R4 by 3 bits to the right
; adds an 8 bit value to register R1
; subtracts an 8 bit value from register R2
; loads an 8 bit immediate into the high byte of Register R3
; compares the low byte of register R4 with an immediate value
; PC = R1, R1 = PC+2
; Trigger IRQ associated with the channel number in R2.L
MC9S12XE-Family Reference Manual Rev. 1.23
; translated to LDL R4,#$34; LDH R4,#$12
; translated to ADDL R4,#$78; ADDH R4,#$56
Chapter 10 XGATE (S12XGATEV3)
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