LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 168

Manufacturer Part Number

KIT STUDENT LEARNING S12 DG128

Manufacturer

Freescale Semiconductor

Architecture

Code Gen Tools Included

Code Warrior

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

HCS12 DG128 Learning Kit

Rohs Compliant

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x0368

Address 0x0369

Write: Anytime.

Write:Never, writes to this register have no effect.

Port R general purpose input/output data—Data Register

Port R pins 7 through 0 are associated with TIM channels TIMIOC7 through TIMIOC0.

When not used with the alternative function, these pins can be used as general purpose I/O.

If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the

buffered pin input state is read.

Port R input data—

This register always reads back the buffered state of the associated pins. This can also be used to detect overload

or short circuit conditions on output pins.

Port R Data Register (PTR)

Port R Input Register (PTIR)

= Unimplemented or Reserved

Table 2-82. PTIR Register Field Descriptions

Table 2-81. PTR Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 2-84. Port R Input Register (PTIR)

Figure 2-83. Port R Data Register (PTR)

u = Unaffected by reset

Access: User read/write

Freescale Semiconductor

Access: User read