LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 320

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 8 S12X Debug (S12XDBGV3) Module
The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
8.3.2.7.2
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in
by setting the comparator enable bit in the associated DBGXCTL control register.
320
Address: 0x0027
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
SC[3:0]
SC[3:0]
0000
0001
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
3–0
SC[3:0]
W
R
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
These bits select the targeted next state whilst in State2, based upon the match event.
0
0
7
Debug State Control Register 2 (DBGSCR2)
= Unimplemented or Reserved
Table 8-23. State1 Sequencer Next State Selection (continued)
Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Figure 8-10. Debug State Control Register 2 (DBGSCR2)
0
0
6
Table 8-25. State2 —Sequencer Next State Selection
Figure 8-1
MC9S12XE-Family Reference Manual , Rev. 1.23
Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2
Table 8-24. DBGSCR2 Field Descriptions
Table 8-42
Match2 triggers to Final State....... Other matches have no effect
Match2 triggers to State3....... Other matches have no effect
5
0
0
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
and described in
dictate that in the case of simultaneous matches, the match
Any match triggers to state1
Any match triggers to state3
0
0
4
Description
Description
Section
Description
SC3
0
3
8.3.2.8.1”. Comparators must be enabled
SC2
2
0
Freescale Semiconductor
SC1
0
1
SC0
0
0