LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 487

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write: Only in special modes
11.3.2.12 S12XECRG COP Timer Arm/Reset Register (ARMCOP)
This register is used to restart the COP time-out period.
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Freescale Semiconductor
Module Base + 0x000B
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
W
R
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
you must write $55 followed by a write of $AA. Other instructions may be executed between these
writes but the sequence ($55, $AA) must be completed prior to COP end of time-out period to
avoid a COP reset. Sequences of $55 writes or sequences of $AA writes are allowed. When the
WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period;
writing any value in the first 75% of the selected period will cause a COP reset.
Bit 7
0
0
7
Bit 6
0
0
6
Figure 11-14. S12XECRG ARMCOP Register Diagram
MC9S12XE-Family Reference Manual Rev. 1.23
Bit 5
5
0
0
Bit 4
0
0
4
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
Bit 3
0
0
3
Bit 2
2
0
0
Bit 1
0
0
1
Bit 0
0
0
0
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