LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 559

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.3.2.23 Input Control Overwrite Register (ICOVW)
Read: Anytime
Write: Anytime
All bits reset to zero.
14.3.2.24 Input Control System Control Register (ICSYS)
Read: Anytime
Write: Once in normal modes
Freescale Semiconductor
Module Base + 0x002A
Module Base + 0x002B
NOVW[7:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7:0
W
W
R
R
NOVW7
SH37
DLY7
No Input Capture Overwrite
0 The contents of the related capture register or holding register can be overwritten when a new input capture
1 The related capture register or holding register cannot be written by an event unless they are empty (see
0
0
7
7
0
0
0
0
0
1
or latch occurs.
Section 14.4.1.1, “IC
latched in the holding register.
DLY6
0
0
0
0
1
1
Table 14-29. Delay Counter Select Examples when PRNT = 1
NOVW6
SH26
Figure 14-46. Input Control Overwrite Register (ICOVW)
0
0
6
6
Figure 14-47. Input Control System Register (ICSYS)
DLY5
0
0
0
1
1
1
MC9S12XE-Family Reference Manual Rev. 1.23
Channels”). This will prevent the captured value being overwritten until it is read or
Table 14-30. ICOVW Field Descriptions
DLY4
NOVW5
SH15
0
0
1
1
1
1
5
0
5
0
DLY3
0
1
1
1
1
1
NOVW4
SH04
0
0
DLY2
4
4
1
1
1
1
1
1
Description
DLY1
NOVW3
1
1
1
1
1
1
TFMOD
0
0
3
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
DLY0
1
1
1
1
1
1
NOVW2
PACMX
1024 bus clock cycles
128 bus clock cycles
256 bus clock cycles
512 bus clock cycles
2
0
2
0
32 bus clock cycles
64 bus clock cycles
Delay
NOVW1
BUFEN
0
0
1
1
NOVW0
LATQ
0
0
0
0
559