LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 60

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 1 Device Overview MC9S12XE-Family
60
Function 1
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
PK[6:4]
PK[3:0]
Name
PM7
PM6
PM5
PM4
PM3
PM2
PM1
PM0
PP7
PP6
PP5
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Pin
Function 2
RXCAN3
RXCAN2
RXCAN1
RXCAN0
TXCAN3
TXCAN2
TXCAN1
TXCAN0
[22:20]
[19:16]
Name
ADDR
ADDR
KWP7
KWP6
KWP5
RXD7
RXD6
RXD5
RXD4
TXD7
TXD6
TXD5
TXD4
Pin
Function 3
ACC[2:0]
RXCAN0
RXCAN0
TXCAN0
TXCAN0
IQSTAT
PWM7
PWM6
PWM5
Name
RXD3
TXD3
[3:0]
Pin
—
—
—
—
—
—
—
—
Table 1-10. Signal Properties Summary (Sheet 3 of 4)
MC9S12XE-Family Reference Manual , Rev. 1.23
Function 4
RXCAN4
RXCAN4
TXCAN4
TXCAN4
MISO0
MOSI2
Name
SCK2
SS0
SS2
Pin
—
—
—
—
—
—
—
—
—
—
—
—
Function 5
TIMIOC7
TIMIOC6
TIMIOC5
MOSI0
Name
SCK0
Pin
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Supply
Power
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
PERM/PPSM Disabled Port M I/O RX of CAN3 and
PERM/PPSM Disabled Port M I/OCAN0, CAN2,
PERM/PPSM Disabled Port M I/O, CAN0, CAN2,
PERM/PPSM Disabled Port M I/O TX of CAN1,
PERM/PPSM Disabled Port M I/O, RX of CAN1,
PERM/PPSM Disabled Port M I/O, TX of CAN0
PERM/PPSM Disabled Port M I/O, RX of CAN0
PERM/
PERL/
PERL/
PERL/
PERL/
PERL/
PERL/
PERL/
PERL/
PERP/
PERP/
PERP/
PUCR
PUCR
PPSM
CTRL
PPSP
PPSP
PPSP
PPSL
PPSL
PPSL
PPSL
PPSL
PPSL
PPSL
PPSL
Internal Pull
Resistor
Disabled Port M I/O, TX of CAN3 and
Disabled Port P I/O, interrupt, channel
Disabled Port P I/O, interrupt, channel
Disabled Port P I/O, interrupt, channel
Reset
State
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Port K I/O, extended
addresses, access source
for external access
Extended address, PIPE
status
Port L I/O, TXD of SCI7
Port LI/O, RXD of SCI7
Port L I/O, TXD of SCI6
Port LI/O, RXD of SCI6
Port L I/O, TXD of SCI5
Port LI/O, RXD of SCI5
Port L I/O, TXD of SCI4
Port LI/O, RXD of SCI4
CAN4, TXD of SCI3
CAN4, RXD of SCI3
CAN4, SCK of SPI0
CAN4, MOSI of SPI0
CAN0, SS of SPI0
CAN0, MISO of SPI0
7 of PWM/TIM , SCK of SPI2
6 of PWM/TIM, SS of SPI2
5 of PWM/TIM, MOSI of
SPI2
Freescale Semiconductor
Description