LFEBS12UB Freescale Semiconductor, LFEBS12UB Datasheet - Page 581

• Manufacturer Part Number: LFEBS12UB
• Description: KIT STUDENT LEARNING S12 DG128
• Manufacturer: Freescale Semiconductor

Specifications of LFEBS12UB

• Architecture: 8/16-bit
• Code Gen Tools Included: Code Warrior
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12D
• Kit Contents: HCS12 DG128 Learning Kit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 15
Inter-Integrated Circuit (IICV3) Block Description
15.1
The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of
connections between devices, and eliminates the need for an address decoder.
This bus is suitable for applications requiring occasional communications over a short distance between a
number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for
further expansion and system development.
The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
15.1.1
The IIC module has the following key features:
Freescale Semiconductor
Revision
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Number
V01.03
V01.04
V01.05
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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Compatible with I2C bus standard
Multi-master operation
Software programmable for one of 256 different serial clock frequencies
Software selectable acknowledge bit
Interrupt driven byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated start signal generation
Acknowledge bit generation/detection
Bus busy detection
Introduction
Revision Date
Features
17 Nov 2006
14 Aug 2007
28 Jul 2006
15.7.1.7/15-603
15.3.1.2/15-584
15.3.1.1/15-583
Sections
Affected
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 15-1. Revision History
- Update flow-chart of interrupt routine for 10-bit address
- Revise Table1-5
- Backward compatible for IBAD bit name
Description of Changes
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