MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1227

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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29.6.2
The MCU can be unsecured in special single chip mode by erasing the Flash module by the following
method:
After the CCIF flag sets to indicate that the mass operation has completed, reset the MCU into special
single chip mode. The BDM secure ROM will verify that the Flash memory is erased and will assert the
UNSEC bit in the BDM status register. This BDM action will cause the MCU to override the Flash security
state and the MCU will be unsecured. All BDM commands will be enabled and the Flash security byte
may be programmed to the unsecure state by the following method:
29.7
29.7.1
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash memory according to
29.7.2
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
29.8
The Flash module can generate an interrupt when all Flash command operations have completed, when the
Flash address, data and command buffers are empty.
Freescale Semiconductor
Flash Address, Data and Command Buffers empty
All Flash commands completed
Reset the MCU into special single chip mode, delay while the erase test is performed by the BDM
secure ROM, send BDM commands to disable protection in the Flash module, and execute a mass
erase command write sequence to erase the Flash memory.
Send BDM commands to execute a word program sequence to program the Flash security byte to
the unsecured state and reset the MCU.
FPROT — Flash Protection Register (see
FCTL - Flash Control Register (see
FSEC — Flash Security Register (see
Resets
Interrupts
Unsecuring the MCU in Special Single Chip Mode using BDM
Flash Reset Sequence
Reset While Flash Command Active
Interrupt Source
Table 29-19. Flash Interrupt Sources
MC9S12XDP512 Data Sheet, Rev. 2.21
Section
Section
Table
Section
(FSTAT register)
(FSTAT register)
Interrupt Flag
29.3.2.8).
29-1:
29.3.2.2).
CBEIF
CCIF
29.3.2.5).
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
(FCNFG register)
(FCNFG register)
Local Enable
CBEIE
CCIE
Global (CCR) Mask
I Bit
I Bit
1229

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