MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 745

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

During BDM hardware accesses and whilst the BDM module is active, S12XCPU monitoring is disabled.
Thus breakpoints, comparators, and bus tracing mapped to the S12XCPU are disabled but XGATE bus
monitoring accessing the S12XDBG registers, including comparator registers, is still possible. While in
active BDM or during hardware BDM accesses, XGATE activity can still be compared, traced and can be
used to generate a breakpoint to the XGATE module. When the S12XCPU enters active BDM Mode
through a BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
20.1.5
20.2
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the
mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation
modes only.
Freescale Semiconductor
Enable
BDM
x
0
0
1
1
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
S12XCPU BUS
XGATE BUS
READ TRACE DATA (DBG READ DATA BUS)
External Signal Description
Block Diagram
Active
BDM
0
1
0
1
x
Secure
MCU
1
0
0
0
0
Table 20-1. Mode Dependent Restriction Summary
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
Figure 20-1. Debug Module Block Diagram
Matches Enabled
MC9S12XDP512 Data Sheet, Rev. 2.21
Comparator
XGATE only
Yes
Yes
Yes
MATCH0
MATCH1
MATCH2
MATCH3
Active BDM not possible when not enabled
Breakpoints
XGATE only
Only SWI
Possible
Yes
Yes
CONTROL
TRIGGER
LOGIC
TAG &
Chapter 20 S12X Debug (S12XDBGV3) Module
TRIGGER
STATE
BREAKPOINT REQUESTS
XGATE only
Possible
Tagging
S12XCPU & XGATE
Yes
Yes
Yes
STATE SEQUENCER
TRACE BUFFER
TAGS
STATE
TRACE
CONTROL
TRIGGER
XGATE only
Possible
Tracing
Yes
Yes
No
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