MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 778

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
CXINF Information Byte
This describes the format of the information byte used only when tracing from S12XCPU or XGATE in
Detail Mode. When tracing from the S12XCPU in Detail Mode, information is stored to the trace buffer
on all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot
of the XGATE program counter. In this case the CSZ and CRW bits indicate the type of access being made
by the S12XCPU, whilst the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free
cycle (no bus acknowledge) or opcode fetch cycle. Similarly when tracing from the XGATE in Detail
Mode, information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The
S12XCPU entry stored on the same line is a snapshot of the S12XCPU program counter. In this case the
XSZ and XRW bits indicate the type of access being made by the XGATE, whilst the CFREE and COCF
bits indicate if the simultaneous S12XCPU cycle is a free cycle or opcode fetch cycle.
780
CFREE
Field
Field
CSD
CVA
CDV
CSZ
7
6
4
7
6
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source Address
1 Destination Address
Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. This is only used
in Normal and Loop1 mode tracing.
0 Source Address
1 Destination Address
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the S12XCPU trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
S12XCPU Free Cycle Indicator — This bit indicates if the stored S12XCPU address corresponds to a free cycle.
This bit only contains valid information when tracing the XGATE accesses in Detail Mode.
0 Stored information corresponds to free cycle
1 Stored information does not correspond to free cycle
Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains
valid information when tracing S12XCPU activity in Detail Mode.
0 Word Access
1 Byte Access
CFREE
Bit 7
Bit 6
CSZ
Table 20-42. CXINF Field Descriptions
Figure 20-26. Information Byte CXINF
Table 20-41. CINF Field Descriptions
CRW
MC9S12XDP512 Data Sheet, Rev. 2.21
Bit 5
COCF
Bit 4
Description
Description
XACK
Bit 3
Bit 2
XSZ
XRW
Bit 1
Freescale Semiconductor
XOCF
Bit 0