MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 783

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.7.4
Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is
always end aligned, independent of internal channel trigger alignment configuration.
20.4.7.5
When this signal asserts tracing is terminated and an immediate forced breakpoints are generated,
depending on the configuration of DBGBRK bits.
20.4.7.6
XGATE software breakpoints have the highest priority. Active tracing sessions are terminated
immediately.
If a TRIG trigger occurs after Begin or Mid aligned tracing has already been triggered by a comparator
instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session
is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a
comparator channel whose BRK = 0, it has no effect, since tracing has already started.
If a comparator tag hit occurs simultaneously with an external TAGHI/TAGLO hit, the state sequencer
enters state0. TAGHI/TAGLO triggers are always end aligned, to end tracing immediately, independent of
the tracing trigger alignment bits TALIGN[1:0].
If a forced and tagged breakpoint coincide, the forced breakpoint occurs too late to prevent the tagged
instruction being loaded into the execution unit. Conversely the taghit is too late to prevent the breakpoint
request in the DBG module. Thus the S12XCPU suppresses the taghit although the tagged instruction is
executed.
Considering the code example below the forced breakpoint is requested when the location COUNTER is
accessed. This is signalled to the S12XCPU when the next (tagged) instruction (NOP) is already in the
execution stage, thus the tagged instruction is carried out but the tagged breakpoint is suppressed. Reading
the PC with BDM READ_PC returns $C008
c000 cf ff 00
c003 a7
c004 72 70 08
c007 a7
00
[BDM firmware commands]
c008 20 01
20.4.7.6.1
Breakpoint operation is dependent on the state of the S12XBDM module. If the S12XBDM module is
active, the S12XCPU is executing out of BDM firmware and S12X breakpoints are disabled. In addition,
while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the
breakpoint will give priority to BDM requests over SWI requests if the breakpoint happens to coincide
with a SWI instruction in the user’s code. On returning from BDM, the SWI from user code gets executed.
Freescale Semiconductor
Breakpoints Via TAGHI Or TAGLO Pin Taghits
Auxilliary Breakpoint Input
S12XDBG Breakpoint Priorities
S12XDBG Breakpoint Priorities And BDM Interfacing
START
MARK
MC9S12XDP512 Data Sheet, Rev. 2.21
LDS
NOP
INC
NOP
BGND
BRA
#$FF00
COUNTER ; Forced breakpoint location = COUNTER
END ; 1st instruction on return from BDM
; Tagged opcode location = MARK
Chapter 20 S12X Debug (S12XDBGV3) Module
785