MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 818

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2
Table 22-3
(IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports.
The configuration bit PS is used for two purposes:
1
2
820
Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
Applicable only on Port P, H, and J.
DDR
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
summarizes the effect on the various configuration bits, data direction (DDR), output level
IO
Register Descriptions
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
All register bits in this module are completely synchronous to internal
clocks during a register read.
RDR
x
x
x
x
x
x
x
0
0
1
1
0
0
1
1
PE
0
1
1
0
0
1
1
x
x
x
x
x
x
x
x
Table 22-3. Pin Configuration Summary
MC9S12XDP512 Data Sheet, Rev. 2.21
PS
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
1
IE
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
NOTE
Input
Input
Input
Input
Input
Input
Input
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Output, full drive to 0
Output, full drive to 1
Output, reduced drive to 0
Output, reduced drive to 1
Function
Disabled
Pull Up
Pull Down
Disabled
Disabled
Pull Up
Pull Down
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Pull Device
Freescale Semiconductor
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Disabled
Disabled
Disabled
Disabled
Falling edge
Rising edge
Falling edge
Rising edge
Interrupt

Related parts for MC9S12XDT256CAA