MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 762

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
Table 20-28
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
764
COMPE
Field
RWE
BRK
SRC
RW
4
3
2
1
0
shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
Break — This bit controls whether a comparator match terminates a debug session immediately,
independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be
enabled using the DBGC1 bits DBGBRK[1:0].
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator. The RW bit is not used if RWE = 0.
0 Write cycle will be matched
1 Read cycle will be matched
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator. This bit is not useful for tagged operations.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
Determines mapping of comparator to S12XCPU or XGATE
0 The comparator is mapped to S12XCPU buses
1 The comparator is mapped to XGATE address and data buses
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
RWE Bit
tracing, if active, is terminated and the module disarmed.
0
0
1
1
1
1
Table 20-27. DBGXCTL Field Descriptions (continued)
Table 20-28. Read or Write Comparison Logic Table
RW Bit
x
x
0
0
1
1
MC9S12XDP512 Data Sheet, Rev. 2.21
RW Signal
0
1
0
1
0
1
Description
RW not used in comparison
RW not used in comparison
Write data bus
Read data bus
Comment
No match
No match
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