DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 100

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 3 MCU Operating Modes
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if
8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P1
part of port F carries bus control signals. Pins P1
reset. They can each be set to output addresses by setting the corresponding bits in the data
direction register (DDR) to 1.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at
least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16
bits and port E becomes a data bus.
3.3.6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
Pins P1
be set to output addresses by setting the corresponding bits in the data direction register (DDR) to
1. Port D functions as a data bus, and part of port F carries bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if any area is
designated as 16-bit access space by the bus controller, 16-bit bus mode is set and port E becomes
a data bus.
3.3.7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
but external addresses cannot be accessed.
All I/O ports are available for use as input-output ports.
Notes: 1. Not used on ROMless version.
Rev. 4.00 Feb 15, 2006 page 74 of 900
REJ09B0291-0400
3
3
2. The upper address pins (A
to P1
to P1
Mode 5 *
Mode 6 *
Mode 7 *
immediately after a reset. To use the upper address pins (A
necessary to first set the corresponding bits in the port 1 data direction register
(P1DDR) to 1.
0
0
, ports A, B, and C function as an address bus, port D function as a data bus, and
, ports A, B, and C function as input ports immediately after a reset. They can each
2
1
1
23
to A
20
) cannot be used as outputs in mode 4 or 5
3
to P1
0
function as inputs immediately after a
23
to A
20
) as outputs, it is