DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 293

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port F Register (PORTF)
PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port
F pins (PF
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and
in software standby mode.
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PF
Pins PF
means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the
corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port.
Modes 3 and 7 *
Setting a PFDDR bit to 1 makes the corresponding port F pin PF
the case of pin PF
7
2
Modes 2, 3, 6, and 7 are not available on the ROMless version.
to PF
to PF
:
:
:
:
:
:
0
) must always be performed on PFDR.
0
PF7DR
are designated as bus control input/output pins (WAIT, BACK, BREQ) by
PF7
R/W
—*
R
7
7
7
0
, the output pin. Clearing the bit to 0 makes the pin an input port.
PF6DR
PF6
R/W
—*
R
6
6
0
PF5DR
PF5
R/W
—*
R
5
5
0
7
to PF
PF4DR
0
PF4
.
—*
R/W
R
4
4
0
Rev. 4.00 Feb 15, 2006 page 267 of 900
PF3DR
PF3
R/W
—*
R
3
3
0
6
PF2DR
to PF
PF2
—*
R/W
R
2
2
0
0
an output port, or in
PF1DR
Section 8 I/O Ports
PF1
REJ09B0291-0400
R/W
—*
R
1
1
0
PF0DR
7
PF0
to PF
—*
R/W
R
0
0
0
0
).