DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 638
![MCU 5V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2345TE20
Manufacturer Part Number
DF2345TE20
Description
MCU 5V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2345TE20V.pdf
(929 pages)
Specifications of DF2345TE20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
71
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2345TE20
HD64F2345TE20
HD64F2345TE20
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas
Quantity:
222
Company:
Part Number:
DF2345TE20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 17 ROM
Rev. 4.00 Feb 15, 2006 page 612 of 900
REJ09B0291-0400
V
FWE
MD
RES
SWE bit
Notes: 1. In transition to the boot mode and transition from the boot mode to another mode, mode switching via RES
CC
2
to MD
Flash memory access disabled period
(x: Wait time after SWE setting)
Flash memory reprogammable period
(Flash memory program execution and data read, other than verify, are disabled.)
2. When making a transition from the boot mode to another mode, the mode programming setup time
3. See section 20.1.6, Flash Memory Characteristics.
0
input is necessary.
During this switching period (period during which a low level is input to the RES pin), the state of the address
dual port and bus control output signals (AS, RD, HUR, LWR) changes.
Therefore, do not use these pins as output signals during this switching period.
t
MDS
(
min) = 200 ns relative to the RES clear timing is necessary.
Mode switching *
(Example: Boot Mode
t
OSC1
SWE set
t
Wait time: x
MDS
t
MDS
1
Figure 17.38 Mode Transition Timing
*
Boot mode
3
Programming and
erase possible
SWE clear
Mode
switching *
t
RESW
Min 0 s
t
User Mode
MDS
*
2
Wait time: x
1
User
mode
Programming
possible
erase
User program mode
and
User Program Mode
Wait
time: x
Programming and
erase possible
User
mode
Wait
time: x
User
program
mode
Programming
possible
erase
and
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