DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 13

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

4.3
4.4
4.5
4.6
4.7
Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
4.2.3
4.2.4
4.2.5
Traces................................................................................................................................ 95
Interrupts ........................................................................................................................... 96
Trap Instruction................................................................................................................. 97
Stack Status after Exception Handling.............................................................................. 98
Notes on Use of the Stack ................................................................................................. 99
Overview........................................................................................................................... 101
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 104
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources............................................................................................................... 109
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 114
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Usage Notes ...................................................................................................................... 124
5.5.1
5.5.2
5.5.3
5.5.4
DTC Activation by Interrupt............................................................................................. 126
5.6.1
5.6.2
5.6.3
Reset Sequence .................................................................................................... 93
Interrupts after Reset............................................................................................ 94
State of On-Chip Supporting Modules after Reset Release ................................. 94
Features................................................................................................................ 101
Block Diagram ..................................................................................................... 102
Pin Configuration................................................................................................. 103
Register Configuration......................................................................................... 103
System Control Register (SYSCR) ...................................................................... 104
Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 105
IRQ Enable Register (IER) .................................................................................. 106
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 107
IRQ Status Register (ISR).................................................................................... 108
External Interrupts ............................................................................................... 109
Internal Interrupts................................................................................................. 110
Interrupt Exception Handling Vector Table......................................................... 110
Interrupt Control Modes and Interrupt Operation ................................................ 114
Interrupt Control Mode 0 ..................................................................................... 117
Interrupt Control Mode 2 ..................................................................................... 119
Interrupt Exception Handling Sequence .............................................................. 121
Interrupt Response Times .................................................................................... 123
Contention between Interrupt Generation and Disabling..................................... 124
Instructions that Disable Interrupts ...................................................................... 125
Times when Interrupts Are Disabled ................................................................... 125
Interrupts during Execution of EEPMOV Instruction.......................................... 126
Overview.............................................................................................................. 126
Block Diagram ..................................................................................................... 127
Operation ............................................................................................................. 127
.......................................................................................... 101
Rev. 4.00 Feb 15, 2006 page xi of xxiv