DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 865

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

TSTR—Timer Start Register
TSYR—Timer Synchro Register
Bit
Initial value
Read/Write
Note:
Bit
Initial value
Read/Write
Notes:
If 0 is written to the CST bit during operation with the TIOC pin designated for output,
the counter stops but the TIOC pin output compare output level is retained. If TIOR
is written to when the CST bit is cleared to 0, the pin output level will be changed to
the set initial output value.
1.
2.
:
:
:
:
:
:
To set synchronous operation, the SYNC bits for at least two channels must
be set to 1.
To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing
source must also be set by means of bits CCLR2 to CCLR0 in TCR.
—
—
7
0
—
—
7
0
—
—
6
0
—
—
6
0
CST5
SYNC5
R/W
Timer Synchronization
R/W
5
0
0
1
5
0
TCNTn operates independently (TCNT presetting/
clearing is unrelated to other channels)
TCNTn performs synchronous operation
TCNT synchronous presetting/synchronous clearing
is possible
CST4
SYNC4
R/W
R/W
4
0
4
0
H'FFC0
H'FFC1
Counter Start
CST3
Rev. 4.00 Feb 15, 2006 page 839 of 900
SYNC3
R/W
0
1
3
0
R/W
3
0
TCNTn count operation is stopped
TCNTn performs count operation
Appendix B Internal I/O Register
CST2
SYNC2
R/W
R/W
2
0
2
0
CST1
SYNC1
R/W
R/W
1
0
REJ09B0291-0400
1
0
(n = 5 to 0)
CST0
(n = 5 to 0)
SYNC0
R/W
R/W
0
0
0
0
TPU
TPU