DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 286

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 8 I/O Ports
8.10.2
Table 8.17 shows the port E register configuration.
Table 8.17 Port E Registers
Name
Port E data direction register
Port E data register
Port E register
Port E MOS pull-up control register
Note:
Port E Data Direction Register (PEDDR)
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Rev. 4.00 Feb 15, 2006 page 260 of 900
REJ09B0291-0400
Bit
Initial value
R/W
Modes 1, 2, 4, 5, and 6 *
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit
to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the
pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is
ignored, and port E is designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller.
Modes 3 and 7 *
Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the
bit to 0 makes the pin an input port.
* Lower 16 bits of the address.
Register Configuration
Modes 2, 3, 6, and 7 are not available on the ROMless version.
:
:
:
PE7DDR
W
7
0
PE6DDR
W
6
0
PE5DDR
PEDDR
PEDR
PEPCR
Abbreviation
PORTE
W
5
0
PE4DDR
W
4
0
PE3DDR
R/W
W
R/W
R
R/W
W
3
0
Initial Value
H'00
H'00
Undefined
H'00
PE2DDR
W
2
0
PE1DDR
W
1
0
H'FEBD
Address *
H'FF6D
H'FF5D
H'FF74
PE0DDR
W
0
0