DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 264

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Section 8 I/O Ports
Port A MOS Pull-Up Control Register (PAPCR)
PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port A on an individual bit basis.
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
Bits 3 to 0 are valid in modes 1, 2, 3, 6, and 7, and all the bits are invalid in modes 4 and 5. When
a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on
the MOS input pull-up for the corresponding pin.
PAPCR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port A Open Drain Control Register (PAODR)
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA
Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified.
All bits are valid in modes 1, 2, 3, and 7. *
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Rev. 4.00 Feb 15, 2006 page 238 of 900
REJ09B0291-0400
Bit
Initial value
R/W
Bit
Initial value
R/W
Modes 2, 3, 6, and 7 are not available on the ROMless version.
:
:
:
:
:
:
3
to PA
Undefined
Undefined
—
—
—
—
7
7
0
).
Undefined
Undefined
—
—
—
—
6
6
Undefined
Undefined
—
—
—
—
5
5
Undefined
Undefined
—
—
—
—
4
4
PA3ODR
PA3PCR
R/W
R/W
3
0
3
0
PA2ODR
PA2PCR
R/W
R/W
2
0
2
0
PA1ODR
PA1PCR
R/W
R/W
1
0
1
0
PA0ODR
PA0PCR
R/W
R/W
0
0
0
0