DF2345TE20 Renesas Electronics America, DF2345TE20 Datasheet - Page 69

• Manufacturer Part Number: DF2345TE20
• Description: MCU 5V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2345TE20

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 71
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2345TE20; HD64F2345TE20

Type
Arithmetic
operations
Instruction
DAA
DAS
MULXU
MULXS
DIVXU
DIVXS
CMP
NEG
EXTU
EXTS
TAS
Size *
B
B/W
B/W
B/W
B/W
B/W/L
B/W/L
W/L
W/L
B
Function
Rd decimal adjust
Decimal-adjusts an addition or subtraction result in a
general register by referring to the CCR to produce 4-bit
BCD data.
Rd
Performs unsigned multiplication on data in two general
registers: either 8 bits
16 bits
Rd
Performs signed multiplication on data in two general
registers: either 8 bits
16 bits
Rd ÷ Rs
Performs unsigned division on data in two general
registers: either 16 bits ÷ 8 bits
remainder or 32 bits ÷ 16 bits
remainder.
Rd ÷ Rs
Performs signed division on data in two general registers:
either 16 bits ÷ 8 bits
or 32 bits ÷ 16 bits
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another
general register or with immediate data, and sets CCR bits
according to the result.
0 – Rd
Takes the two's complement (arithmetic complement) of
data in a general register.
Rd (zero extension)
Extends the lower 8 bits of a 16-bit register to word size, or
the lower 16 bits of a 32-bit register to longword size, by
padding with zeros on the left.
Rd (sign extension)
Extends the lower 8 bits of a 16-bit register to word size, or
the lower 16 bits of a 32-bit register to longword size, by
extending the sign bit.
@ERd – 0, 1
Tests memory contents, and sets the most significant bit
(bit 7) to 1.
Rs
Rs
32 bits.
32 bits.
Rd
Rd
Rd
Rd
Rd
(<bit 7> of @Erd)
Rev. 4.00 Feb 15, 2006 page 43 of 900
Rd
16-bit quotient and 16-bit remainder.
Rd
Rd
8 bits
8 bits
8-bit quotient and 8-bit remainder
16-bit quotient and 16-bit
16 bits or 16 bits
16 bits or 16 bits
8-bit quotient and 8-bit
REJ09B0291-0400
Section 2 CPU